1. Field of the Invention
The present invention relates to a delta sigma modulating apparatus applied to a delta sigma analog-to-digital (AD) converter used in the fields of audio, communications and the like. More specifically, the present invention relates to a delta sigma modulating apparatus in which two or more stages of delta sigma modulators are cascaded together.
2. Prior Art
Over sampling AD converters frequently called delta sigma AD converters have previously been known. Delta sigma AD converters convert analog signals into digital signals at an extremely high over sampling rate and perform noise shaping to push noise away to a high frequency region, and after the noise shaping, perform digital filtering processing. By this, delta sigma AD converters can realize a higher effective resolution than the quantization output of delta sigma converters. Thereafter, the effective sampling rate is returned to a Nyquist rate by use of decimation.
FIG. 2 is a block diagram showing a typical cascade-type delta sigma AD converter. In FIG. 2, reference designations A1, A2 and A3 represent delta sigma modulators. The delta sigma modulators A1, A2 and A3 which comprise first- or second-order delta sigma modulators are cascaded together, and an analog input AIN is externally supplied to the delta sigma modulator A1 in the first stage.
It is known that first- or second-order delta sigma modulators are stable. Therefore, by cascading a plurality of first- or second-order delta sigma modulators and using a high-order modulator as a result, the effect of noise shaping is enhanced to thereby reduce the noise level of the pass band.
Reference designations Δ1 and Δ2 represent differentiators that differentiate the output signals of the delta sigma modulators A1 and A2, respectively. Reference designation F represents an adder that subtracts the output signals of the differentiators Δ1 and Δ2 from the output signal of the delta sigma modulator A1 in the first stage. Reference designation DF represents a digital decimation filter that performs decimation processing on the output signal of the adder F. Reference designation T represents a delay element that delays the output signal of the digital decimation filter DF. A digital output DOUT is obtained from the delay element D.
As described above, the differentiators Δ1 and Δ2 and the adder F are provided and the output signal of the delta sigma modulator A1 in the first stage and the differential signals of the output signals of the delta sigma modulators A2 and A3 in the second and third stages are added together. By this, the quantization noise of the delta sigma modulator A1 in the preceding stage is deleted, the quantization noise A3 in the last stage is pushed away to a high frequency region, and then, the noise that is pushed away to the high-frequency side is removed by the digital decimation filter DF. Consequently, a high signal-to-noise ratio can be realized.
FIG. 3 is a block diagram showing an example of the prior art delta sigma modulating apparatus. This delta sigma modulating apparatus comprises two stages of second-order delta sigma modulators (noise shaping circuits) that are cascaded together. This art is described, for example, in Japanese Published Patent Application H08-028666 and U.S. Pat. No. 5,061,928.
In FIG. 3, reference numeral 1 represents an input terminal, reference numerals 3, 6, 14, 17, 26 and 28 represent adders, reference numerals 5, 7, 16 and 18 represent integrators, and reference numerals 8 and 19 represent quantizers. Reference numerals 100 and 101 represent digital-to-analog (DA) converters. Reference numerals 11, 12, 13, 21, 22 and 25 represent computing elements, reference numerals 9 and 10 represent delay elements, and reference numerals 23 and 24 represent differentiators. Reference numeral 27 represents an output terminal.
The adder 3 subtracts the analog signal outputted from the DA converter 100, from the analog signal added through the input terminal 1. The integrator 5 integrates the analog signal outputted from the adder 3. The adder 6 subtracts the analog signal outputted from the DA converter 100, from the analog signal outputted from the integrator 5. The integrator 7 integrates the analog signal outputted from the adder 6. The quantizer 8 outputs a digital signal corresponding to the analog signal outputted from the integrator 7. The DA converter 100 outputs an analog signal corresponding to the digital output signal of the quantizer 8, and inputs it to the adders 3 and 6.
The computing element 11, which determines the amount of analog feedback from the quantizer 8 to the adder 3, multiplies the analog output signal of the DA converter 100 by a1 times, and inputs the result to the adder 3. The computing element 12, which determines the amount of analog feedback from the quantizer 8 to the adder 6, multiplies the analog output signal of the DA converter 100 by a2 times, and inputs the result to the adder 6.
The adder 28 subtracts the analog signal outputted from the DA converter 100, from the analog signal outputted from the integrator 7.
The delta sigma modulator A1 in the first stage is thus structured.
The computing element 13 performs scaling to multiply the analog signal outputted from the adder 28 by 1/c time and output the result. The adder 14 subtracts the analog signal outputted from the DA converter 101, from the analog signal outputted from the computing element 13. The integrator 16 integrates the analog signal outputted from the adder 14. The adder 17 subtracts the analog signal outputted from the DA converter 101, from the analog signal outputted from the integrator 16. The integrator 18 integrates the analog signal outputted from the adder 17. The quantizer 19 outputs a digital signal corresponding to the analog signal outputted from the integrator 18. The DA converter 101 outputs an analog signal corresponding to the digital output signal of the quantizer 19, and inputs it to the adders 14 and 17.
The computing element 21, which determines the amount of analog feedback from the quantizer 19 to the adder 14, multiplies the analog output signal of the DA converter 101 by a3 times, and inputs the result to the adder 14. The computing element 22, which determines the amount of analog feedback from the quantizer 19 to the adder 17, multiplies the analog output signal of the DA converter 101 by a4 times, and inputs the result to the adder 17.
The delta sigma modulator A2 in the second stage is thus structured.
The delay elements 9 and 10 which are cascaded together delay the digital output signal of the quantizer 8 by two clocks. The differentiators 23 and 24 which are cascaded together differentiate the analog output signal of the quantizer 19. The differentiator Δ1 is thus structured.
The computing element 25 performs scaling to multiply the output signal of the differentiator Δ1 by c times and output the result.
The adder 26 adds the output signal of the delay element 10 and the output signal of the computing element 25 together, and supplies the result to the output terminal 27.
In the above structure, the delta sigma modulating apparatus operates as follows: The signal obtained by multiplying the analog output signal of the DA converter 100 by a1 times by the computing element 11 is subtracted, by the adder 3, from the analog input signal added to the input terminal 1. The analog output signal of the adder 3 is integrated by the integrator 5.
The signal obtained by multiplying the analog output signal of the DA converter 100 by a2 times by the computing element 12 is subtracted from the analog output signal of the integrator 5 by the adder 6. The analog output signal of the adder 6 is integrated by the integrator 7.
The output signal of the differentiator 7 is analog-to-digital converted by the quantizer 8, and inputted to the adder 26 via the delay elements 9 and 10.
The analog output signal of the DA converter 100 is subtracted from the output signal of the integrator 7 by the adder 28. By this, only the quantization noise of the quantizer 1 is added to the delta sigma modulator (second-order noise shaping modulator) in the second stage. At this time, the output signal of the adder 28 is scaled by the computing element 13. That is, the voltage level of the output signal of the adder 28 is reduced to 1/c (c>1) by the computing element 13.
Then, the signal obtained by multiplying the analog output signal of the DA converter 101 by a3 times by the computing element 21 is subtracted, by the adder 14, from the analog signal scaled by the computing element 13. The analog output signal of the adder 14 is integrated by the integrator 16.
The signal obtained by multiplying the analog output signal of the DA converter 101 by a4 times by the computing element 22 is subtracted from the analog output signal of the integrator 16 by the adder 17. The analog output signal of the adder 17 is integrated by the integrator 18.
The output signal of the integrator 18 is analog-to-digital converted by the quantizer 19 and differentiated by the differentiators 23 and 24, and then, multiplied by c times by the computing element 25 that performs scaling and inputted to the adder 26.
Then, the output signal of the delay element 10 and the output signal of the computing element 25 are added together by the adder 26, and the result is outputted from the output terminal 27.
Here, the part from the input terminal 1 to the output of the quantizer 8 constitutes the second-order delta sigma modulator A1. Moreover, the part from the input of the computing element 13 to the output of the quantizer 19 constitutes the second-order delta sigma modulator A2.
When the input of the delta sigma modulator A1 is X, the output thereof is y1, the output of the delta sigma modulator A2 is y2, the quantization noise of the quantizer 8 is E1, the quantization noise of the quantizer 19 is E2, the values of the gain coefficients a1 and a2 of the computing elements 11 and 21 are both 1 and the values of the gain coefficients a2 and a4 of the computing elements 12 and 22 are both 2, the output y1 of the delta sigma modulator A1 is expressed by the following expression (1):y1=z−2X+(1−Z−1)2E1  (1)
On the other hand, the output y2 of the quantizer 19 is expressed by the following expression (2):y2=−Z−2E1/C+(1−Z−1)2E2  (2)
Moreover, the output y3 of the computing element 25 constituting the scaling factor is expressed by the following expression (3):y3=−(1−Z−1)2Z−2E1+C(1−Z−1)4E2  (3)
Therefore, the output y that appears at the output terminal 27 is expressed by the following condition (4):y=Z−4X+C(1−Z−1)4E2  (4)
As is well known to persons skilled in the art, the quantization noise of the output is only the quantization noise of the quantizer 19 in the succeeding stage that is shaped to a fourth-order high frequency region.
FIG. 4 is a block diagram showing another prior art. This example is described in Japanese Laid-Open Patent Application No. H 07-202707. Although detailed description thereof is omitted, a difference from FIG. 3 is that the adder 28 in cascading the delta sigma modulator A1 in the first stage to the delta sigma modulator A2 in the second stage is deleted, a digital adder 29A is provided instead and similar processing to that performed by the adder 28 is performed by the digital adder 29A. This reduces the number of capacitors, so that the manufacturing cost can be reduced.
Conventionally, in cascade-type delta sigma modulators, to achieve excellent resolution, it is necessary that the characteristics of the delta sigma modulators strictly coincide with each other. In particular, when the characteristics of analog parts are not strictly matched, undeleted quantization noise leaks into the pass band.
As the analog circuit of the delta sigma modulator, typically, a switched capacitor circuit is frequently used, and it is known that the characteristics are degraded by a mismatch between capacitors. To suppress such characteristic degradation, that is, to secure a large margin, the order of the delta sigma modulator is made higher.
Description will be given with reference to FIG. 3. When the input is X and the output of the quantizer 8 is y1, the following expression (5) holds:y1={Z−2X+(1−Z−1)2E1}/{1+(a2−2)Z−1+(1+a1−a2)Z−2}  (5)
Further, when the output of the quantizer 19 is y2, the following expression (6) holds:y2={−Z−2E1/C+(1−Z−1)2E2}/{1+(a4−2)Z−1+(1+a3−a4)Z−2}  (6)
Therefore, the output y of the adder 26 is expressed by the following expression (7):
                                                        y              =                            ⁢                                                                    Z                                          -                      2                                                        ⁢                  y1                                +                                                      C                    ⁡                                          (                                              1                        -                                                  Z                                                      -                            1                                                                                              )                                                        ⁢                  y2                                                                                                        =                            ⁢                                                {                                                            Z                                              -                        4                                                              +                                                                                                                        Z                                                          -                              2                                                                                ⁡                                                      (                                                          1                              -                                                              Z                                                                  -                                  1                                                                                                                      )                                                                          2                                            ⁢                      E1                                                        }                                /                                                                                                      ⁢                                                {                                      1                    +                                                                  (                                                  a2                          -                          2                                                )                                            ⁢                                              Z                                                  -                          1                                                                                      +                                                                  (                                                  1                          +                          a1                          -                          a2                                                )                                            ⁢                                              Z                                                  -                          2                                                                                                      }                                +                                  (                                      1                    -                                          Z                                              -                        1                                                                              )                                                                                                                      ⁢                                                {                                                                                    -                                                  Z                                                      -                            2                                                                                              ⁢                      E1                                        +                                                                                            C                          ⁡                                                      (                                                          1                              -                                                              Z                                                                  -                                  1                                                                                                                      )                                                                          2                                            ⁢                      E2                                                        }                                /                                                                                                      ⁢                              {                                  1                  +                                                            (                                              a4                        -                        2                                            )                                        ⁢                                          Z                                              -                        1                                                                              +                                                            (                                              1                        +                        a3                        -                        a4                                            )                                        ⁢                                          Z                                              -                        2                                                                                            }                                                                        (        7        )            
Here, paying attention to the coefficient k=Δy/ΔE1 of the term of the quantization noise E1, the following expression (8) is obtained:k=Z−3(1−Z−1)2[(a4−a2)+(a3−a1−a4+a2)Z−1]/[1+(a2−2)Z−1+(1+a1−a2)Z−2]{1+(a4−2)Z−1+(1+a3−a4)Z−2}  (8)
Here, when a4=a2=2 and a3=a1=1, k is zero, and the expression (7) coincides with the expression (4). However, assuming now that a4−a2=a3−a1=ΔA, the following expression (9) is obtained:k=ΔAZ−3(1−Z−1)2/[1+(a2−2)Z−1+(1+a1−a2)Z−2]{1+(a4−2)Z−1+(1+a3−a4)Z−2}  (9)
Therefore, it is understood that, although the effect of fourth-order noise shaping is originally expected, only second-order noise shaping in which the quantization noise E1 is attenuated is performed and characteristics are degraded. This also applies to FIG. 4.